An asynchronous interface may be employed to exchange signals between multiple clock domains. In such instances, it is often difficult to verify that the asynchronous interface functions properly across various alignments of the multiple clocks running at different frequencies. In many cases, such verification does not occur. For example, when signals traveling across an interface experience different delays (e.g., due to differing logic, wiring or other delays), a signal “launched” across the interface first may actually be latched at a receiving side of the interface by a clock cycle that occurs after a clock cycle employed to latch a subsequently transmitted signal. Behavioral simulations, gate-level simulations and static timing tools all may have difficulty modeling such conditions. Accordingly, conventional modeling typically cannot predict whether a state machine on a receiving side of an asynchronous interface will function under “real world” conditions that may produce signal transmission failures.
A need therefore exists for asynchronous interface methods and apparatus that can simulate the actual failing conditions of an interface, and/or that allow such failing conditions to be mitigated and/or eliminated.